As well known in the art, a dynamic random access memory system (hereinafter referred to as dynamic memory system) is composed of memory cells each consisting of one, two or three metal-oxide-semiconductor (MOS) transistors and a single data storage capacitor. A memory system of this type is preferred for realizing a data storage device of a large capacity for its potential possibility of high density integration on a semiconductor chip. The logic state of each cell of such a dynamic memory system is determined depending upon the quantity of positive charges, accumulated on the capacitor forming part of the cell. Thus, if the cell has positive charges stored on the capacitor thereof, the cell may represent a logic "0" state and, with no positive charge stored on the capacitor, the cell may represent a logic "1" state. The cell in a logic "0" state is in a thermally equilibrium condition while the cell in a logic "1" state is in a thermally non-equilibrium condition. Transition from the logic "1" state to the logic "0"state thus occurs in the cell in few milliseconds to several seconds. To compensate for the charges which are thus allowed to leak from the cell, the cell must be refreshed periodically at time intervals of, typically, two to three milliseconds. The requirement for such refresh operation is one of the most important causes which make a dynamic type memory device inconvenient for practical use.
One approach to providing a solution to such a problem in a dynamic memory system is to have a built-in refresh control circuitry located on the semiconductor chip on which the dynamic memory system is formed. Such a built-in refresh control circuitry typically includes a refresh timing circuit to generate refresh clock pulses and a refresh address counter responsive to the clock pulses generated by the timing circuit. The timing circuit generates refresh pulses at a predetermined frequency so that the refresh address counter is enabled to refresh the cells of the system in a fully automated fashion. A problem however still remains in a memory system of this nature primarily due to the extreme difficulties encountered in testing the refresh address counter to check if the register is operating properly.
In a dynamic semiconductor memory device furnished with such a fully automated built-in refresh control circuitry in lieu of an external or off-chip refresh control circuit, the refresh operation is started and the timing circuit begins to generate refresh clock pulses automatically when the device is switched in. Such fully automated operation of the refresh control circuitry makes it extremely difficult to check the refresh address counter for proper operation and for this reason makes it necessary to additionally provide a refresh terminal through which to control the internal timing circuit of the device.
It is, accordingly, an important object of the present invention to provide a dynamic memory system having a fully automated built-in refresh control circuitry and an internal, viz., on-chip circuit for testing the refresh address counter in the control circuitry without having recourse to the provision of an additional refresh terminal on the semiconductor chip on which the memory system is fabricated.